The inventive concepts relate to recognition apparatuses, recognition methods, mounting apparatuses, and/or mounting methods.
Japanese Patent Publication No. hei 7-320062 describes, when a semiconductor chip is mounted to a circuit board, a grasp posture of the semiconductor chip while being carried toward the circuit board is recognized. In a recognition apparatus disclosed in Japanese Patent Publication No. hei 7-320062, a bottom surface of a ball grid array type package is imaged, and a gradient of the image of solder balls is measured, thereby recognizing the posture of the package. At this time, the position of the semiconductor chip is estimated from a plurality of center of gravity positions of the solder balls in the image, by linear fitting using a least-square method.
Japanese Patent Publication No. 2005-93839 describes that recognition accuracy is improved by enhancing contrast in a captured image, in position recognition of a plurality of solder bumps included in a semiconductor chip.
Japanese Patent Publication No. 2011-75310 describes a configuration in which lens magnification with respect to a test object having a cyclic pattern is finely adjusted.
In recognition apparatuses described in, for instance, Japanese Patent Publication No. hei 7-320062 and Japanese Patent Publication No. 2005-93839, a semiconductor chip is imaged using an imaging sensor having a plurality of imaging pixels. A recognition process is performed on a plurality of formations on the semiconductor chip, for instance, a solder bump included in the captured image. A connection portion formed in the semiconductor chip, for instance, the solder bump, becomes smaller. Accordingly, if the numbers of pixels of the imaging sensors are identical, as the connection portion decreases in size, the number of pixels allocated for each solder bump or for each pitch between the solder bumps also decreases. Accordingly, the following problems may arise due to, for instance, a decrease of the size of the connection portion.
The accuracy of position recognition in a case where the arrangement of the solder bumps conforms to image sampling may be lower than that in a case where the arrangement of the solder bumps does not conform to the image sampling. Here, the case where the arrangement of the solder bumps conforms to the image sampling means that the number of imaging pixels corresponding to each pitch of the arrangement of the solder bumps is constantly maintained. Assuming that a position at which the number of pixels are set to a peak corresponds to the position of the center (the position of a peak) of the solder bump and that two pixels have a peak value (or a value close thereto) on average in the vicinity of the center of the solder bump, when the arrangement of the solder bumps conforms with the image sampling, there is the possibility that two pixels constantly (or, constantly and repeatedly) have values close to the peak value with respect to the plurality of solder bumps. When the arrangement of the solder bumps and the image sampling do not conform to each other, however, there is a high possibility that variations may occur for each solder bump such that, for example, one to three pixels have a peak value. Accordingly, an error in position recognition is less than two pixels when the arrangement of the solder bumps and the image sampling conform to each other, and is less than one to three pixels when the arrangement of the solder bumps and the image sampling do not conform to each other. For example, when a plurality of solder bumps having an error of less than one pixel are present, a deviation of the position or direction of each solder bump may be estimated with a high level of accuracy. Therefore, the accuracy of position recognition in a case where the arrangement of the solder bumps conforms to the image sampling may be lower than the accuracy of position recognition in a case where the arrangement of the solder bumps does not conform to the image sampling.